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1 features ? 32-mbit dataflash and 4-mbit sram single 62-ball (8 mm x 12 mm x 1.2 mm) cbga package 2.7v to 3.3v operating voltage dataflash single 2.7v to 3.3v supply serial peripheral interface (spi) compatible 20 mhz max clock frequency page program operation ? single cycle reprogram (erase and program) ? 8192 pages (528 bytes/page) main memory supports page and block erase operations two 528-byte sram data buffers ? allows receiving of data while reprogramming of nonvolatile memory continuous read capability through entire array ? ideal for code shadowing applications low power dissipation ? 4 ma active read current typical ? 2 a cmos standby current typical hardware data protection feature industrial temperature range sram 4-megabit (256k x 16) 2.7v to 3.3v v cc 70 ns access time fully static operation and tri-state output 1.2v (min) data retention industrial temperature range 32-megabit dataflash ? + 4-megabit sram stack memory AT45BR3214B rev. 3356a?dflash?2/04
2 AT45BR3214B 3356a?dflash?2/04 pin configuration AT45BR3214B (top view) pin name function cs chip select sck serial clock si serial input so serial output wp write protect reset reset rdy/busy ready busy vcc flash power supply gnd flash ground a0 - a17 sram address input i/o0 - i/o15 sram data inputs/outputs slb sram lower byte sub sram upper byte svcc sram power sgnd sram ground scs1 sram chip select 1 scs2 sram chip select 2 swe sram write enable soe sram output enable nc no connect a b c d e f g h 1 2345678910 nc nc si a16 wp sgnd nc slb so nc a11 a8 rdy/busy reset nc sub a17 a5 a15 a10 nc soe a7 a4 a14 a9 i/o11 a6 a0 a13 i/o15 i/o13 i/o12 i/o9 a3 cs a12 swe i/o6 scs2 i/o10 i/o8 a2 gnd gnd i/o14 i/o4 svcc i/o2 i/o0 a1 sck nc i/o7 i/o5 vcc i/o3 i/o1 scs1 nc nc nc
3 AT45BR3214B 3356a?dflash?2/04 block diagram description the AT45BR3214B combines a 32-megabit dataflash (32m x 1) and a 4-megabit sram (organized as 256k x 16) in a stacked 62-ball cbga package. the stacked mod- ule operates at 2.7v to 3.3v in the industrial temperature range. 32-mbit dataflash 4-mbit sram address data (i/o0 - i/o15) reset cs sck rdy/busy scs1 scs2 wp swe soe si so absolute maximum ratings temperature under bias ................................. -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -55 c to +150 c all input voltages (including nc pins) with respect to ground .....................................-0.2v to +3.3v all output voltages with respect to ground .....................................-0.2v to +0.2v dc and ac operating range AT45BR3214B operating temperature (case) industrial -40 c - 85 c v cc power supply 2.7v to 3.3v
4 AT45BR3214B 3356a?dflash?2/04 32-mbit dataflash description the 32-mbit dataflash is a 2.7-volt only, serial interface flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. in addi- tion to the main memory, the 32-mbit dataflash also contains two sram data buffers of 528 bytes each. the buffers allow receiving of data while a page in the main memory is being reprogrammed, as well as reading or writing a continuous data-stream. eeprom emulation (bit or byte alterability) is easily handled with a self-contained three step read-modify-write operation. unlike conventional flash memories that are accessed randomly with multiple address lines and a parallel interface, the dataflash uses a spi serial interface to sequentially access its data. dataflash supports spi mode 0 and mode 3. the simple serial interface facilitates hardware layout, increases system reli- ability, minimizes switching noise, and reduces package size and active pin count. the device is optimized for use in many comm ercial and industrial app lications where high density, low pin count, low voltage, and low power are essential. the device operates at clock frequencies up to 20 mhz with a typical active read current consumption of 4 ma. to allow for simple in-system reprogrammability, the 32-mbit dataflash does not require high input voltages for programming. the device operates from a single power supply, 2.7v to 3.3v, for both the program and read operations. the 32-mbit dataflash is enabled through the chip select pin (cs ) and accessed via a three-wire interface con- sisting of the serial input (si), serial output (so), and the serial clock (sck). all programming cycles are self-timed, and no separate erase cycle is required before programming. when the device is shipped from atmel, the most significant page of the memory array may not be erased. in other words, the contents of the last page may not be filled with ffh. dataflash block diagram memory array to provide optimal flexibility, the memory array of the 32-mbit dataflash is divided into three levels of granularity comprising of sectors, blocks, and pages. the memory archi- tecture diagram illustrates the breakdown of each level and details the number of pages per sector and block. all program operations to the dataflash occur on a page-by-page basis; however, the optional erase operations can be performed at the block or page level. flash memory array page (528 bytes) buffer 2 (528 bytes) buffer 1 (528 bytes) i/o interface sck cs reset vcc gnd rdy/busy wp so si
5 AT45BR3214B 3356a?dflash?2/04 memory architecture diagram device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in tables 1 through 4. a valid instruction starts with the falling edge of cs followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. while the cs pin is low, tog- gling the sck pin controls the loading of the opcode and the desired buffer or main memory address location through the si (serial input) pin. all instructions, addresses and data are transferred with the most significant bit (msb) first. buffer addressing is referenced in the datasheet using the terminology bfa9 - bfa0 to denote the ten address bits required to desi gnate a byte address within a buffer. main memory addressing is referenced using the terminology pa12 - pa0 and ba9 - ba0 where pa12 - pa0 denotes the 13 address bits required to designate a page address and ba9 - ba0 denotes the ten address bits required to designate a byte address within the page. read commands by specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers. the dataflash supports two categories of read modes in relation to the sck signal. the differences between the modes are in respect to the inactive state of the sck signal as well as which clock cycle data will begin to be output. the two categories, which are comprised of four modes total, are defined as inactive clock polarity low or inactive clock polarity high and spi mode 0 or spi mode 3. a separate opcode (refer to table 1 on page 11 for a complete list) is used to select which category will be used for reading. please refer to the ?detailed bit-level read timing? diagrams in this datasheet for details on the clock cycle sequences for each mode. continuous array read: by supplying an initial starting address for the main memory array, the continuous array read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. the dataflash incorporates an internal address counter that will automatically increment on every clock sector 0 = 4224 bytes (4k + 128) sector 1 = 266,112 bytes (252k + 8064) sector 15 = 270,336 bytes (256k + 8k) block = 4224 bytes (4k + 128) 8 pages sector 0 sector 1 page = 528 bytes (512 + 16) page 0 page 1 page 6 page 7 page 8 page 9 page 8190 page 8191 block 0 page 14 page 15 page 16 page 17 page 18 page 8189 block 1 sector architecture block architecture page architecture block 0 block 1 block 62 block 63 block 64 block 65 block 1022 block 1023 block 126 block 127 block 128 block 129 sector 2 sector 2 = 270,336 bytes (256k + 8k) sector 16 = 270,336 bytes (256k + 8k) block 2
6 AT45BR3214B 3356a?dflash?2/04 cycle, allowing one continuous read operation without the need of additional address sequences. to perform a continuous read, an opcode of 68h or e8h must be clocked into the device followed by 24 address bits and 32 don?t care bits. the first bit of the 24-bit address sequence is reserved for upward and downward compatibility to larger and smaller density devices (see notes under ?command sequence for read/write operations? diagram). the next 13 address bits (pa12 - pa0) specify which page of the main memory array to read, and the last ten bits (ba9 - ba0) of the 24-bit address sequence specify the starting byte address within the page. the 32 don?t care bits that follow the 24 address bits are needed to initialize the read operation. following the 32 don?t care bits, additional clock pulses on the sck pin will result in serial data being out- put on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bits, the don?t care bits, and the reading of data. when the end of a page in main memory is reached during a continuous array read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). when the last bit in the main memory array has been read, the device will continue reading back at the begin- ning of the first page of memory. as with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. a low-to-high transition on the cs pin will terminate the read operation and tri-state the so pin. the maximum sck frequency allowable for the continuous array read is defined by the f car specification. the continuous array read bypasses both data buff- ers and leaves the contents of the buffers unchanged. main memory page read: a main memory page read allows the user to read data directly from any one of the 8192 pages in the main memory, bypassing both of the data buffers and leaving the contents of t he buffers unchanged. to start a page read, an opcode of 52h or d2h must be clocked into the device followed by 24 address bits and 32 don?t care bits. the first bit of the 24-bit address sequence is a reserved bit, the next 13 address bits (pa12 - pa0) specify the page address, and the next ten address bits (ba9 - ba0) specify the starting byte address within the page. the 32 don?t care bits which follow the 24 address bits are sent to initialize the read operation. following the 32 don?t care bits, additional pulses on sck result in serial data being output on the so (serial output) pin. the cs pin must remain low during the loading of the opcode, the address bits, the don?t care bits, and the reading of data. when the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginning of the same page. a low-to-high transition on the cs pin will terminate the read operation and tri-state the so pin. buffer read: data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. an opcode of 54h or d4h is used to read data from buffer 1, and an opcode of 56h or d6h is used to read data from buffer 2. to perform a buffer read, the eight bits of the opcode must be followed by 14 don?t care bits, ten address bits, and eight don?t care bits. since the buffer size is 528 bytes, ten address bits (bfa9 - bfa0) are required to specify the first byte of data to be read from the buffer. the cs pin must remain low during the loading of the opcode, the address bits, the don?t care bits, and the reading of data. when the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. a low-to-high transi- tion on the cs pin will terminate the read operation and tri-state the so pin. status register read: the status register can be used to determine the device?s ready/busy status, the result of a main memory page to buffer compare operation, or the device density. to read the status regi ster, an opcode of 57h or d7h must be
7 AT45BR3214B 3356a?dflash?2/04 loaded into the device. after the last bit of the opcode is shifted in, the eight bits of the status register, starting with the msb (bit 7), will be shifted out on the so pin during the next eight clock cycles. the five most signific ant bits of the status register will contain device information, while the remaining three least-significant bits are reserved for future use and will have undefined values. after bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as cs remains low and sck is being tog- gled) starting again with bit 7. the data in the status register is constantly updated, so each repeating sequence will output new data. ready/busy status is indicated using bit 7 of the status register. if bit 7 is a 1, then the device is not busy and is ready to accept the next command. if bit 7 is a 0, then the device is in a busy state. the user can cont inuously poll bit 7 of the status register by stopping sck at a low level once bit 7 has been output. the status of bit 7 will continue to be output on the so pin, and once the device is no longer busy, the state of so will change from 0 to 1. there are eight operati ons which can cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer com- pare, buffer to main memory page program with built-in erase, buffer to main memory page program without built-in erase, page erase, block erase, main memory page program, and auto page rewrite. the result of the most recent main memory page to buffer compare operation is indi- cated using bit 6 of the status register. if bit 6 is a 0, then the data in the main memory page matches the data in the buffer. if bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. the device density is indicated using bits 5, 4, 3 and 2 of the status register. for the 32- mbit dataflash, the four bits are 1, 1, 0 and 1. the decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of serial dataflash devices, allowing a total of sixteen dif- ferent density configurations. program and erase commands buffer write: data can be shifted in from the si pin into either buffer 1 or buffer 2. to load data into either buffer, an 8-bit opcode, 84h for buffer 1 or 87h for buffer 2, must be followed by 14 don?t care bits and ten address bits (bfa9 - bfa0). the ten address bits specify the first byte in the buffer to be written. the data is entered following the address bits. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will continue to be loaded into the buffer until a low-to- high transition is detected on the cs pin. buffer to main memory page program with built-in erase: data written into either buffer 1 or buffer 2 can be programmed into the main memory. to start the operation, an 8-bit opcode, 83h for buffer 1 or 86h for buffer 2, must be followed by one reserved bit, 13 address bits (pa12 - pa0) that specify the page in the main memory to be written, and ten additional don?t care bits. when a low-to-high transition occurs on the cs pin, the part will first erase the selected page in main memory to all 1s and then pro- gram the data stored in the buffer into the specified page in the main memory. both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp1101xx
8 AT45BR3214B 3356a?dflash?2/04 buffer to main memory page program without built-in erase: a previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. to start the operation, an 8-bit opcode, 88h for buffer 1 or 89h for buffer 2, must be followed by the one reserved bit, 13 address bits (pa12 - pa0) that specify the page in the main memory to be written, and ten additional don?t care bits. when a low-to-high transition occurs on the cs pin, the part will program the data stored in the buffer into the specified page in the main memory. it is necessary that the page in main memory that is being programmed has been previously erased. the pro- gramming of the page is internally self-timed and should take place in a maximum time of t p . during this time, the status register will indicate that the part is busy. successive page programming operations without doing a page erase are not recom- mended. in other words, changing bytes within a page from a ?1? to a ?0? during multiple page programming operations without erasing that page is not recommended. pag e er a se : the optional page erase command can be used to individually erase any page in the main memory array allowing the buffer to main memory page program without built-in erase command to be utilized at a later time. to perform a page erase, an opcode of 81h must be loaded into the device, followed by one reserved bit, 13 address bits (pa12 - pa0), and ten don?t care bits. the 13 address bits are used to specify which page of the memory array is to be erased. when a low-to-high transition occurs on the cs pin, the part will erase the selected page to 1s. the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the status register will indicate that the part is busy. block erase: a block of eight pages can be erased at one time allowing the buffer to main memory page program without built-in erase command to be utilized to reduce programming times when writing large amounts of data to the device. to perform a block erase, an opcode of 50h must be loaded into the device, followed by one reserved bit, ten address bits (pa12 - pa3), and 13 don?t care bits. the ten address bits are used to specify which block of eight pages is to be erased. when a low-to-high tran- sition occurs on the cs pin, the part will erase the selected block of eight pages to 1s. the erase operation is internally self-timed and should take place in a maximum time of t be . during this time, the status register will indicate that the part is busy. block erase addressing pa 12 pa 1 1 pa 1 0 pa 9 pa 8 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 b l ock 0 0 0 0000000xxx 0 0 0 0 0000001xxx 1 0 0 0 0000010xxx 2 0 0 0 0000011xxx 3 1 1 1 1111100xxx1020 1 1 1 1111101xxx1021 1 1 1 1111110xxx1022 1 1 1 1111111xxx1023
9 AT45BR3214B 3356a?dflash?2/04 main memory page program through buffer: this operation is a combina- tion of the buffer write and buffer to main memory page program with built-in erase operations. data is first shifted into buffer 1 or buffer 2 from the si pin and then pro- grammed into a specified page in the main memory. to initiate the operation, an 8-bit opcode, 82h for buffer 1 or 85h for buffer 2, must be followed by one reserved bit and 23 address bits. the 13 most significant address bits (pa12 - pa0) select the page in the main memory where data is to be written, and the next ten address bits (bfa9 - bfa0) select the first byte in the buffer to be written. after all address bits are shifted in, the part will take data from the si pin and store it in one of the data buffers. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low-to-high transition on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the programming of the page are internally self-timed and should take place in a maximum of time t ep . during this time, the status register will indicate that the part is busy. additional commands main memory page to buffer transfer: a page of data can be transferred from the main memory to either buffer 1 or buffer 2. to start the operation, an 8-bit opcode, 53h for buffer 1 and 55h for buffer 2, must be followed by one reserved bit, 13 address bits (pa12 - pa0) which specify the page in main memory that is to be trans- ferred, and ten don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode, the address bits, and the don?t care bits from the si pin. the transfer of the page of data from the main memory to the buffer will begin when the cs pin transi- tions from a low to a high state. during the transfer of a page of data (t xfr ), the status register can be read to determine whether the transfer has been completed or not. main memory page to buffer compare: a page of data in main memory can be compared to the data in buffer 1 or buffer 2. to initiate the operation, an 8-bit opcode, 60h for buffer 1 and 61h for buffer 2, must be followed by 24 address bits consisting of one reserved bit, 13 address bits (pa12 - pa0) which specify the page in the main mem- ory that is to be compared to the buffer, and ten don?t care bits. the cs pin must be low while toggling the sck pin to load the opcode, the address bits, and the don?t care bits from the si pin. on the low-to-high transition of the cs pin, the 528 bytes in the selected main memory page will be compared with the 528 bytes in buffer 1 or buffer 2. during this time (t xfr ), the status register will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register is updated with the result of the compare. auto page rewrite: this mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. to start the rewrite operation, an 8-bit opcode, 58h for buffer 1 or 59h for buffer 2, must be followed by one reserved bit, 13 address bits (pa12 - pa0) that specify the page in main memory to be rewritten, and ten additional don?t care bits. when a low- to-high transition occurs on the cs pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy.
10 AT45BR3214B 3356a?dflash?2/04 if a sector is programmed or reprogrammed sequentially page-by-page, then the pro- gramming algorithm shown in figure 1 on page 28 is recommended. otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in figure 2 on page 29 is recommended. each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector. operation mode summary the modes described can be separated into two groups ? modes which make use of the flash memory array (group a) and modes which do not make use of the flash memory array (group b). group a modes consist of: 1. main memory page read 2. main memory page to buffer 1 (or 2) transfer 3. main memory page to buffer 1 (or 2) compare 4. buffer 1 (or 2) to main memory page program with built-in erase 5. buffer 1 (or 2) to main memory page program without built-in erase 6. page erase 7. block erase 8. main memory page program through buffer 9. auto page rewrite group b modes consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status register read if a group a mode is in progress (not fully completed) then another mode in group a should not be started. however, during this time in which a group a mode is in progress, modes in group b can be started. this gives the serial dataflash the ability to virtually accommodate a continuous data- stream. while data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). see application note an-4 (?using atmel?s serial dataflash?) for more details. pin descriptions serial input (si): the si pin is an input-only pin and is used to shift data into the device. the si pin is used for all data input including opcodes and address sequences. serial output (so): the so pin is an output-only pin and is used to shift data out from the device. serial clock (sck): the sck pin is an input-only pin and is used to control the flow of data to and from the dataflash. data is always clocked into the device on the rising edge of sck and clocked out of the device on the falling edge of sck. chip select (cs ): the dataflash is selected when the cs pin is low. when the device is not selected, data will not be accepted on the si pin, and the so pin will remain in a high-impedance state. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition on the cs pin is required to end an operation.
11 AT45BR3214B 3356a?dflash?2/04 write protect: if the wp pin is held low, the first 256 pages of the main memory cannot be reprogrammed. the only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. if this pin and feature are not utilized it is recommended that the wp pin be driven high externally. reset : a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. if this pin and feature are not utilized it is recommended that the reset pin be driven high externally. ready/busy : this open drain output pin will be driven low when the device is busy in an internally self-timed operation. this pin, which is normally in a high state (through a1k ? external pull-up resistor), will be pulled low during programming operations, com- pare operations, and during page-to-buffer transfers. the busy status indicates that the flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. power-on/reset state when power is first applied to the device, or when recovering from a reset condition, the device will default to spi mode 3. in addition, the so pin will be in a high-impedance state, and a high-to-low transition on the cs pin will be required to start a valid instruc- tion. the spi mode will be automatically selected on every falling edge of cs by sampling the inactive clock state. after power is applied and vcc is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started. table 1. read commands command sck mode opcode continuous array read inactive clock polarity low or high 68h spi mode 0 or 3 e8h main memory page read inactive clock polarity low or high 52h spi mode 0 or 3 d2h buffer 1 read inactive clock polarity low or high 54h spi mode 0 or 3 d4h buffer 2 read inactive clock polarity low or high 56h spi mode 0 or 3 d6h status register read inactive clock polarity low or high 57h spi mode 0 or 3 d7h
12 AT45BR3214B 3356a?dflash?2/04 note: in tables 2 and 3, an sck mode designation of ?any? denotes any one of the four modes of operation (inactive clock polarit y low, inactive clock polarity high, spi mode 0, or spi mode 3). table 2. program and erase commands command sck mode opcode buffer 1 write any 84h buffer 2 write any 87h buffer 1 to main memory page program with built-in erase any 83h buffer 2 to main memory page program with built-in erase any 86h buffer 1 to main memory page program without built-in erase any 88h buffer 2 to main memory page program without built-in erase any 89h page erase any 81h block erase any 50h main memory page program through buffer 1 any 82h main memory page program through buffer 2 any 85h table 3. additional commands command sck mode opcode main memory page to buffer 1 transfer any 53h main memory page to buffer 2 transfer any 55h main memory page to buffer 1 compare any 60h main memory page to buffer 2 compare any 61h auto page rewrite through buffer 1 any 58h auto page rewrite through buffer 2 any 59h
13 AT45BR3214B 3356a?dflash?2/04 note: r = reserved bit p = page address bit b = byte/buffer address bit x = don?t care table 4. detailed bit-level addressing sequence opcode opcode address byte address byte address byte additional don?t care bytes required 50h 01010000r pppppppppp xxxxxxxxxxxxx n/a 52h 01010010r pppppppppppppbbb bbbbbbb 4 bytes 53h 01010011r ppppppppppppp xxxxxxxxxx n/a 54h 01010100xxxxxxxxxxxxxx bbbbbbbbbb 1 byte 55h 01010101r ppppppppppppp xxxxxxxxxx n/a 56h 01010110xxxxxxxxxxxxxx bbbbbbbbbb 1 byte 57h 01010111 n/a n/a n/a n/a 58h 01011000r ppppppppppppp xxxxxxxxxx n/a 59h 01011001r ppppppppppppp xxxxxxxxxx n/a 60h 01100000r ppppppppppppp xxxxxxxxxx n/a 61h 01100001r ppppppppppppp xxxxxxxxxx n/a 68h 01101000r pppppppppppppbbb bbbbbbb 4 bytes 81h 10000001r ppppppppppppp xxxxxxxxxx n/a 82h 10000010r pppppppppppppbbb bbbbbbb n/a 83h 10000011r ppppppppppppp xxxxxxxxxx n/a 84h 10000100xxxxxxxxxxxxxx bbbbbbbbbb n/a 85h 10000101r pppppppppppppbbb bbbbbbb n/a 86h 10000110r ppppppppppppp xxxxxxxxxx n/a 87h 10000111xxxxxxxxxxxxxx bbbbbbbbbb n/a 88h 10001000r ppppppppppppp xxxxxxxxxx n/a 89h 10001001r ppppppppppppp xxxxxxxxxx n/a d2h 11010010r pppppppppppppbbb bbbbbbb 4 bytes d4h 11010100xxxxxxxxxxxxxx bbbbbbbbbb 1 byte d6h 11010110xxxxxxxxxxxxxx bbbbbbbbbb 1 byte d7h 11010111 n/a n/a n/a n/a e8h 11101000r pppppppppppppbbb bbbbbbb 4 bytes r eserve d pa 12 pa 11 pa 10 pa 9 pa8 pa7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 ba 9 ba 8 ba7 ba6 ba 5 ba 4 ba 3 ba 2 ba 1 ba 0
14 AT45BR3214B 3356a?dflash?2/04 note: 1. after power is applied and v cc is at the minimum specified datasheet value, the system should wait 20 ms before an opera- tional mode is started. note: 1. i cc1 during a buffer read is 20ma maximum. absolute maximum ratings* temperature under bias ............................... -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v dc and ac operating range 32-mbit dataflash operating temperature (case) com. 0 c to 70 c ind. -40 c to 85 c v cc power supply (1) 2.7v to 3.3v dc characteristics symbol parameter condition min typ max units i sb standby current cs , reset , wp = v cc , all inputs at cmos levels 210a i cc1 (1) active current, read operation f = 20 mhz; i out = 0 ma; v cc = 3.3v 410ma i cc2 active current, program/erase operation v cc = 3.3v 15 35 ma i li input load current v in = cmos levels 1 a i lo output leakage current v i/o = cmos levels 1 a v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v
15 AT45BR3214B 3356a?dflash?2/04 ac characteristics symbol parameter 32-mbit dataflash units min max f sck sck frequency 20 mhz f car sck frequency for continuous array read 20 mhz t wh sck high time 22 ns t wl sck low time 22 ns t cs minimum cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns t csb cs high to rdy/busy low 200 ns t su data in setup time 5 ns t h data in hold time 10 ns t ho output hold time 0 ns t dis output disable time 18 ns t v output valid 20 ns t xfr page to buffer transfer/compare time 250 s t ep page erase and programming time 20 ms t p page programming time 14 ms t pe page erase time 8ms t be block erase time 12 ms t rst reset pulse width 10 s t rec reset recovery time 1 s
16 AT45BR3214B 3356a?dflash?2/04 input test waveforms and measurement levels t r , t f < 3 ns (10% to 90%) output test load ac waveforms two different timing diagrams are shown below. waveform 1 shows the sck signal being low when cs makes a high-to-low transition, and waveform 2 shows the sck sig- nal being high when cs makes a high-to-low transition. both waveforms show valid timing diagrams. the setup and hold times for the si signal are referenced to the low-to- high transition on the sck signal. waveform 1 shows timing that is also compatible with spi mode 0, and waveform 2 shows timing that is compatible with spi mode 3. waveform 1 ? inactive clock polarity low and spi mode 0 waveform 2 ? inactive clock polarity high and spi mode 3 ac driving levels ac measurement level 0.45v 2.0 0.8 2.4v device under test 30 pf cs sck si so t css valid in t h t su t wh t wl t csh t cs t v high impedance valid out t ho t dis high impedance cs sck si so t css valid in t h t su t wl t wh t csh t cs t v high z valid out t ho t dis high impedance
17 AT45BR3214B 3356a?dflash?2/04 reset timing (inactive cl ock polarity low shown) note: the cs signal should be in the high state before the reset signal is deasserted. command sequence for read/write operations (except status register read) notes: 1. ?r? designates bits reserved for larger densities. 2. it is recommended that ?r? be a logical ?0? for densities of 32m bits or smaller. 3. for densities larger than 32m bits, the ?r? bits become the most significant page address bit for the appropriate density. cs sck reset so high impedance high impedance si t rst t rec t css si cmd 8 bits 8 bits 8 bits msb reserved for larger densities page address (pa12-pa0) byte/buffer address (ba9-ba0/bfa9-bfa0) lsb r x x x x x x x x x x x x x x x x x x x x x x x
18 AT45BR3214B 3356a?dflash?2/04 write operations the following block diagram and waveforms illustrate the various write sequences available. main memory page program through buffers buffer write buffer to main memory page program (data from buffer programmed into flash page) flash memory array page (528 bytes) buffer 2 (528 bytes) buffer 1 (528 bytes) i/o interface si buffer 1 to main memory page program main memory page program through buffer 2 buffer 2 to main memory page program main memory page program through buffer 1 buffer 1 write buffer 2 write si cmd n n+1 last byte completes writing into selected buffer starts self-timed erase/program operation cs r , pa12-6 pa5-0, bfa9-8 bfa7-0 si cmd x xx, bfa9-8 bfa7-0 n n+1 last byte completes writing into selected buffer cs si cmd pa5-0, xx x cs starts self-timed erase/program operation r , pa12-6 each transition represents 8 bits and 8 clock cycles n = 1st byte read n+1 = 2nd byte read
19 AT45BR3214B 3356a?dflash?2/04 read operations the following block diagram and waveforms illustrate the various read sequences available. main memory page read main memory page to buffer transfer (data from flash page read into buffer) buffer read flash memory array page (528 bytes) buffer 2 (528 bytes) buffer 1 (528 bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read so si cmd pa5-0, ba9-8 ba7-0 x xxx cs n n+1 so r , pa12-6 si cmd pa5-0, xx x starts reading page data into buffer cs so r , pa12-6 si cmd x xx, bfa9-8 bfa7-0 cs n n+1 so x e ach transition represents 8 bits and 8 clock cycles n = 1st byte read n+1 = 2nd byte read
20 AT45BR3214B 3356a?dflash?2/04 detailed bit-level read timing ? inactive clock polarity low continuous array re ad (opcode: 68h) main memory page read (opcode: 52h) si 0 1xx cs so sck 12 63 64 65 66 67 68 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 data out bit 0 of page n+1 bit 4223 of page n lsb msb t su t v si 0 1 0 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v
21 AT45BR3214B 3356a?dflash?2/04 detailed bit-level read timing ? inactive clock polarity low (continued) buffer read (opcode: 54h or 56h) status register read (opcode: 57h) si 0 1 0 10 xxx cs so sck 12345 36 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v si 0 1 0 10 111 cs so sck 12345 78910 11 12 16 17 high-impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 1 d 0 d 7 lsb msb
22 AT45BR3214B 3356a?dflash?2/04 detailed bit-level read timing ? inactive clock polarity high continuous array re ad (opcode: 68h) main memory page read (opcode: 52h) si 0 1xxx cs so sck 12 63 64 65 66 67 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 bit 0 of page n+1 bit 4223 of page n lsb msb t su t v data out si 0 1 0 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 68
23 AT45BR3214B 3356a?dflash?2/04 detailed bit-level read timing ? inactive clock polarity high (continued) buffer read (opcode: 54h or 56h) status register read (opcode: 57h) si 0 1 0 10 xxx cs so sck 12345 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 44 si 0 1 0 10 111 cs so sck 12345 78910 11 12 17 18 high-impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 4 d 0 d 7 lsb msb d 6
24 AT45BR3214B 3356a?dflash?2/04 detailed bit-level read timing ? spi mode 0 continuous array re ad (opcode: e8h) main memory page read (opcode: d2h) si 1 1xxx cs so sck 12 62 63 64 65 66 67 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 data out bit 0 of page n+1 bit 4223 of page n lsb msb t su t v si 1 1 0 10 xxx cs so sck 12345 60 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4
25 AT45BR3214B 3356a?dflash?2/04 detailed bit-level read timing ? spi mode 0 (continued) buffer read (opcode: d4h or d6h) status register read (opcode: d7h) si 1 1 0 10 xxx cs so sck 12345 36 37 38 39 40 41 42 43 xx high-impedance command opcode t su d 7 d 6 d 5 data out msb t v d 4 si 1 1 0 10 111 cs so sck 12345 78910 11 12 16 17 high-impedance status register output command opcode msb t su 6 d 1 d 0 d 7 lsb msb d 7 d 6 d 5 t v d 4
26 AT45BR3214B 3356a?dflash?2/04 detailed bit-level read timing ? spi mode 3 continuous array re ad (opcode: e8h) main memory page read (opcode: d2h) si 1 1xxx cs so sck 12 63 64 65 66 67 high-impedance d 7 d 6 d 5 d 2 d 1 d 0 d 7 d 6 d 5 bit 0 of page n+1 bit 4223 of page n lsb msb t su t v data out si 1 1 0 10 xxx cs so sck 12345 61 62 63 64 65 66 67 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 68
27 AT45BR3214B 3356a?dflash?2/04 detailed bit-level read timing ? spi mode 3 (continued) buffer read (opcode: d4h or d6h) status register read (opcode: d7h) si 1 1 0 10 xxx cs so sck 12345 37 38 39 40 41 42 43 xx high-impedance d 7 d 6 d 5 data out command opcode msb t su t v d 4 44 si 1 1 0 10 111 cs so sck 12345 78910 11 12 17 18 high-impedance d 7 d 6 d 5 status register output command opcode msb t su t v 6 d 4 d 0 d 7 lsb msb d 6
28 AT45BR3214B 3356a?dflash?2/04 figure 1. algorithm for sequentially programming or reprogramming the entire array notes: 1. this type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by- page. 2. a page can be written using either a main memory page program operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. start main memory page program through buffer (82h, 85h) end provide address and data buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
29 AT45BR3214B 3356a?dflash?2/04 figure 2. algorithm for randomly modifying data notes: 1. to preserve data integrity, each page of a dataflash sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations. 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite portions of the flash array. low-power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all pages of the sector. see application note an-4 (?using atmel?s serial dataflash?) for more details. sector addressing pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 sector 0 0 0 0000000 0 0000xxxxxx1 0001xxxxxx2 0010xxxxxx3 1100xxxxxx13 1101xxxxxx14 1110xxxxxx15 1111xxxxxx16 start main memory page to buffer transfer (53h, 55h) increment page address pointer (2) auto page rewrite (2) (58h, 59h) end provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array main memory page program through buffer (82h, 85h) buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
30 AT45BR3214B 3356a?dflash?2/04 4-megabit sram description the 4-megabit sram is a high-speed, super low-power cmos sram organized as 256k words by 16 bits. the sram uses high-performance full cmos process technol- ogy and is designed for high-speed and low-powe r circuit technology. it is particularly well-suited for the high-density low-power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2v. features fully static operation and tri-state output ttl compatible inputs and outputs battery backup ? 1.2v (min) data retention block diagram voltage (v) speed (ns) operation current/i cc (ma) (max) standby current (a) (max) temperature ( c) 2.7 - 3.3 70 3 10 -40 - 85 memory array 256k x 16 i/o0 sub slb soe scs2 scs1 swe data i/o buffer sense amp write driver i/o7 i/o8 i/o15 row decoder column decoder block decoder pre decoder add input buffer a0 a17
31 AT45BR3214B 3356a?dflash?2/04 note: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. notes: 1. h = v ih , l = v il , x = don't care (v il or v ih ) 2. sub , slb (upper, lower byte enable). these active low inputs allow individual bytes to be written or read. when slb is low, data is written or read to the lower byte, i/o0 - i/o7. when sub is low, data is written or read to the upper byte, i/o8 - i/o15. note: 1. undershoot: v il = -1.5v for pulse width less than 30 ns. undershoot is sampled, not 100% tested. absolute maximum ratings (1) symbol parameter rating unit v in , v out input/output voltage -0.3 to 3.6 v v cc power supply -0.3 to 3.6 v t a operating temperature -40 to 85 c t stg storage temperature -55 to 150 c p d power dissipation 1.0 w truth table scs1 scs2 swe soe slb (2) sub (2) mode i/o pin power i/o0 - i/o7 i/o8 - i/o15 h (1) x xx xx deselected high-z high-z standby x (1) l xx hh l (1) hhh lh output disabled high-z high-z active hl ll lhlx lh write d in high-z active hl high-z d in ll d in d in d in high-z lhhl lh read d out high-z active hl high-z d out ll d out d out d out high-z recommended dc operating condition symbol parameter min typ max unit v cc supply voltage 2.7 3.0 3.3 v v ss ground 0 0 0 v v ih input high voltage 2.2 v cc + 0.3 v v il (1) input low voltage -0.3 (1) 0.6 v
32 AT45BR3214B 3356a?dflash?2/04 note: 1. these parameters are sampled and not 100% tested. dc electrical characteristics t a = -40 c to 85 c symbol parameter test condition min max unit i li input leakage current v ss < v in < v cc -1 1 a i lo output leakage current v ss < v out < v cc , scs1 = v ih or scs2=v il or soe = v ih or swe = vil or sub = v ih , slb = v ih -1 1 a i cc operating power supply current scs1 = v il , scs2=v ih , v in = v ih or v il , i i/o = 0 ma 3ma i cc1 average operating current scs1 = v il , scs2 = v ih , v in = v ih or v il , cycle time = min 100% duty, i i/o = 0 ma 15 ma scs1 < 0.2v, scs2 > v cc - 0.2v v in < 0.2v or v in > v cc - 0.2v, cycle time = 1 s 100% duty, i i/o = 0 ma 2ma i sb standby current (ttl input) scs1 = v ih or scs2 = v il or sub , slb = v ih v in = v ih or v il 300 a i sb1 standby current (cmos input) scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 10 a v ol output low i ol = 2.1 ma 0.4 v v oh output high i oh = -1.0 ma 2.4 v capacitance (1) (temp = 25 c, f = 1.0 mhz) symbol parameter condition max unit c in input capacitance (add, scs1 , scs2, slb , sub , swe , soe ) v in = 0 v 8 pf c out output capacitance (i/o) v i/o = 0 v 10 pf
33 AT45BR3214B 3356a?dflash?2/04 ac characteristics t a = -40 c to 85 c, unless otherwise specified # symbol parameter 70 ns unit min max 1t rc read cycle time 70 ns 2t aa address access time 70 ns 3t acs chip select access time 70 ns 4t oe output enable to output valid 35 ns 5t ba slb , sub access time 70 ns 6t clz chip select to output in low z 10 ns 7t olz output enable to output in low z 5 ns 8t blz slb , sub enable to output in low z 10 ns 9t chz chip deselection to output in high z 0 25 ns 10 t ohz out disable to output in high z 0 25 ns 11 t bhz slb , sub disable to output in high z 0 25 ns 12 t oh output hold from address change 10 ns 13 t wc write cycle time 30 ns 14 t cw chip selection to end of write 30 ns 15 t aw address valid to end of write 30 ns 16 t bw slb , sub valid to end of write 30 ns 17 t as address setup time 0 ns 18 t wp write pulse width 30 ns 19 t wr write recovery time 0 ns 20 t whz write to output in high z 0 5 ns 21 t dw data to write time overlap 25 ns 22 t dh data hold from write time 0 ns 23 t ow output active from end of write 5 ns ac test conditions ta = - 4 0 c to 85 c, unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5 ns input and output timing reference level 1.5v output load t clz , t olz , t blz , t chz , t ohz , t bhz , t whz , t ow cl = 5 pf + 1 ttl load others cl = 30 pf + 1 ttl load
34 AT45BR3214B 3356a?dflash?2/04 ac test loads note: including jig and scope capacitance. d out 1728 ohm cl 1029 ohm v tm = 2.8v (1)
35 AT45BR3214B 3356a?dflash?2/04 timing diagrams read cycle 1 (1) , (4) read cycle 2 (1) , (2) , (4) read cycle 3 (1) , (2) , (4) note: 1. read cycle occurs whenever a high on the swe and soe is low, while sub and/or slb and scs1 and scs2 are in active status. 2. soe = v il . 3. transition is measured 200 mv from steady state voltage. this parameter is sampled and not 100% tested. 4. scs1 in high for the standby, low for active. scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address soe sub, slb scs1 scs2 data out high-z data valid t aa t rc t ba t acs t oe t olz t blz t clz t bhz t chz t oh t ohz (3) (3) (3) (3) (3) (3) data out address t aa previous data t oh data valid t oh t rc sub, slb scs1 scs2 data out t acs t clz (3) data valid t chz (3)
36 AT45BR3214B 3356a?dflash?2/04 write cycle 1 (swe controlled) (1) , (4) , (8) write cycle 2 (scs1 , scs2 controlled) (1) , (4) , (8) notes: 1. a write occurs during the overlap of a low swe , a low scs1 , a high scs2 and a low sub and/or slb . 2. t wr is measured from the earlier of scs1 , slb , sub , or swe going high or scs2 going low to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the scs1 , slb and sub low transition and scs2 high transition occur simultaneously with the swe low transition or after the swe transition, outputs remain in a high impedance state. 5. q (data out) is the same phase with the write data of this write cycle. 6. q (data out) is the read data of the next address. 7. transition is measured 200 mv from steady state. this parameter is sampled and not 100% tested. 8. scs1 in high for the standby, low for active scs2 in low for the standby, high for active. sub and slb in high for the standby, low for active. address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t whz t wr t dw t dh t ow data valid high-z t as (2) (5) (5) (3)(7) address swe sub, slb data in scs1 scs2 data out t wc t cw t aw t bw t wp t as t wr t dw t dh data valid high-z (2) high-z
37 AT45BR3214B 3356a?dflash?2/04 notes: 1. typical values are under the condition of t a = 25 c. typical values are sampled and not 100% tested. 2. t rc is read cycle time. data retention timing diagram 1 data retention timing diagram 2 data retention electric characteristic t a = -40 c to 85 c symbol parameter test condition min typ max unit v dr v cc for data retention scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 1.2 3.3 v i ccdr data retention current vcc=1.5v, scs1 > v cc - 0.2v or scs2 < v ss + 0.2v or sub , slb > v cc - 0.2v v in > v cc - 0.2v or v in < v ss + 0.2v 0.2 6 a t cdr chip deselect to data retention time see data retention timing diagram 0 ns t r operating recovery time t rc ns data retention mode t r t cdr vcc scs1 > vcc - 0.2v 2.7v ih vdr scs1 vss vcc 2.7v vdr scs2 vss 0.4v data retention mode t r t cdr scs2 < 0.2v
38 AT45BR3214B 3356a?dflash?2/04 ordering information dataflash f sck (mhz) sram t acc (ns) ordering code dataflash sram package operation range 20 70 AT45BR3214B-c1 32m x 1 256k x 16 62c1 industrial (-40 c to 85 c) package type 62c1 62-ball, plastic chip-scale ball grid array (cbga)
39 AT45BR3214B 3356a?dflash?2/04 packaging information 62c1 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 62c1 , 62-ball (10 x 8 array), 12 x 8 x 1.2 mm body, 0.8 mm ball plastic chip-scale ball grid array package (cbga) a 62c1 05/12/03 side view top view bottom view a b c d e f g h 1 2 3 4 5 6 7 8 9 1.20 ref 2.40 ref 10 marked a1 identifier d e d1 e1 e e ?b a a1 0.12 seating plane c c a1 ball corner common dimensions (unit of measure = mm) symbol min nom max note a ? ? 1.20 a1 0.25 ? ? d 11.90 12.00 12.10 d1 7.20 typ e 7.90 8.00 8.10 e1 5.60 typ e 0.80 typ ? b 0.40 typ
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